1. Technical Field
This invention relates to the fabrication of semiconductor devices. More particularly, it relates to the fabrication of interconnection metallurgy systems atop the semicondutor devices.
2. Background Art
Advances in modern semiconductor device technology have allowed increasing numbers of devices and circuits to be fabricated within a single semicondutor chip. This has required increasing microminiaturization of the interconnection metallurgy system connecting the elements within the chip into circuits. Such miniaturization results in decreased costs and improved performance in integrated circuits but is constantly crowding the fabrication technology, particularly the photolithographic and etching techniques of the interconnection metallurgy.
In integrated circuit design, for example, thousands of impurity regions are conventionally fabricated in a silicon chip, approximately 125-200 mils square. Such regions form transistors, diodes, resistors and the like which are then connected together by thin film wiring patterns atop the chip to form various circuits and for connection to input-output terminals.
This interconnection thin film system atop the chip is extremely complex and usually employs two or three separate levels of complex conductive patterns, each separated by one or more layers of dielectric material. Ordinarily, the first level conductive pattern on the chip surface interconnects the transistors, resistors, diodes, etc. into circuits and also provides for circuit-to-circuit connections. The second level conductive pattern conventionally completes the circuit-to-circuit connections and makes contact to I/O terminals which are connectable to a support such as a module, substrate or card. Alternatively, a third level may be required for power and I/O connections. Four levels of metallization may be required in future products.
At present, the formation of such thin film patterns is accomplished primarily by etching in the presence of etch-resistant photoresist layers. The process involves the traditional photolithographic wet-etching of both the thin film as well as the photoresist layers.
These relatively old and well-known techniques have been eminently successful. However, with the continued miniaturization of semiconductor integrated circuits to achieve greater component density and smaller units of large scale integrated circuitry, the art is rapidly approaching a point where wet etching may become impractical for providing the minute resolution required for the fine line definition of metallization.
Wet etching of thin films may be used in either electron beam or optical exposure systems. However, it often results in the contamination of the metal, primarily due to particles within the etching solution itself. In addition to the purity and composition of the etchant, the duration of the etching must be carefully controlled to prevent under or over-etching of the thin film.
Dry etching, in particular plasma or reactive ion etching, has in relatively recent times come to be recognized as a practical alternative to wet etching. Contamination may be less of a problem; and the etching equipment assures adequate process control of the most precise thin film patterns.
One of the problems associated with plasma etching of thin films, however, is that most of the well-known and commonly used optical and electron beam resist materials cannot withstand the processing intact. The resists tend to flow during the etching process, apparently because of their reactions with the gaseous ions and the temperature of the semiconductor substrate, typically around 200.degree. C. or more. Thus, it would be desirable to be able to plasma etch a single photoresist material directly over a metallic thin film to define the desired conductive pattern. The resist would then be used as a mask and the exposed metal etched away, typically by another gas which attacks the metal but not the photoresist. The remaining photoresist would then be removed in the conventional manner to leave the desired thin film pattern.
To our knowledge there is no practical way to accomplish this. A number of different resist materials and reactive gases have been tried, but with little success.
One alternative solution to this problem is described in U.S. Pat. No. 4,092,442, issued in the names of R. K. Agnihotri and H. C. Kluge. They found that a polyimide mask can withstand the conditions of reactive ion etching, which conditions cause other common resist materials to disintegrate. They use this property by depositing the polyimide layer atop the thin film layer or layers, followed by the application of the resist layer. Both the resist and polyimide layers are exposed. The resist is developed, and the polyimide is etched, thereby exposing portions of the underlying thin film layer. The exposed portions of the thin film are then etched in a plasma gas. The action of the plasma gas also removes the remaining resist layer. The polyimide layer protects the unexposed thin film from attack by the plasma gas.
Although successful, the process of Agnihotri and Kluge requires the added steps of applying, exposing and removing the polyimide. These add to the cost of manufacturing process and are potential detractors from the product yield.